Complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) technology involves the formation of n-channel FETs (NMOS) and p-channel FETs (PMOS) to form low current and high performance integrated circuits. These devices contain a substrate having various electrically isolated active areas that are separated by regions of insulating material such as shallow trench isolation (STI) features or field oxide isolation (FOX). A gate oxide which is normally silicon dioxide is grown on the substrate in active areas and then a polysilicon gate electrode is formed on the gate oxide. Ion implantation is then typically used to form source/drain regions in the substrate adjacent to the channel which is below the electrode and gate oxide. For example, boron can be implanted to form p-channels and arsenic can be implanted to form n-channels. The final steps in the process of forming the device consist of depositing an insulating layer on the substrate and forming contacts to the source/drain regions and to the gate electrodes.
The thickness of the gate oxide is critical to the performance of the device. There is a constant need for thinner oxides to allow a higher speed device with lower power consumption. Current technology requires gate oxide thicknesses of about 50 Angstroms or less. One concern associated with a thin gate oxide is that it will not be thick enough to prevent migration of impurities such as boron dopant from occurring between the gate electrode and channel regions which will degrade the device performance. U.S. Pat. No. 6,197,647 describes a method of depositing a thin gate oxide thickness of 5 to 15 Angstroms followed by deposition of a polysilicon layer that contains nitrogen to inhibit the migration of impurities across the gate oxide layer.
For ultra thin silicon dioxide gates, leakage current will increase tremendously as thickness is reduced. This will cause a large current in the standby mode (IOFF) and a large standby power consumption, thereby making products with these devices commercially unacceptable.
Another concern associated with thin gate oxides is that an excessively high voltage applied to the gate electrode can cause a gate breakdown resulting in a short circuit between the gate electrode and source region. A thicker gate oxide will allow a higher breakdown voltage but at the expense of a slower speed for the circuit. To partially alleviate the thickness requirement, a dual gate oxide technology has been developed that consists of thicker oxides in circuits such as I/O applications where higher speed is not needed. A higher voltage of about 5 V can be applied and the thicker oxide will provide good reliability. A second gate oxide thickness that is thinner than the first is used to form integrated circuits that require high speed. These circuits typically operate at a lower voltage of about 2 V.
U.S. Pat. No. 6,261,972 mentions that dual oxide thicknesses can be formed by means of a nitridation of the substrate in active areas where growth of a thinner oxide thickness is desired. The two different oxide thicknesses are grown simultaneously in the same chamber because growth on the nitrogen implanted active area is retarded compared to growth on an active area without a nitrogen implant. A drawback to this approach is that after nitrogen is introduced into the active channel region in the silicon substrate, significant mobility degradation occurs. U.S. Pat. Nos. 6,080,682 and 6,232,244 also involve nitridation of a substrate and deposition of a blocking layer to prevent loss of nitrogen during a subsequent annealing process in formation of dual gate oxide thicknesses. Nitridation also has a negative impact on the quality of the silicon interface with silicon dioxide.
In U.S. Pat. No. 6,171,911, a method of forming a dual gate oxide is described. Gate oxides are formed in separate steps and a second thinner oxide thickness is grown after removing a previous thicker growth in regions where a thinner thickness is desired. Another feature of this patent is that the annealing step is performed in a hydrogen atmosphere to reduce the native oxide thickness and improve its quality. A native oxide of 10 Angstroms or less generally forms on a substrate if the surface is exposed to air. Contaminants are removed in the annealing process and the layer is densified from about 10 Angstroms to about 4 Angstroms with improved uniformity.
Oxides are generally grown in a thermal oxidation furnace using a dry oxygen ambient at a temperature of between 600° C. and 800° C. Other methods of forming thin thermal oxides are by RTO (rapid thermal oxidation) or by ISSG (in-situ steam generation).
With the introduction of system on a chip (SOC) technology, there is a need to form multiple gate oxide thicknesses on a substrate to enable the fabrication of multiple circuits with different functions that can all perform at once. For example, circuits for I/O connections with a relatively thick gate oxide of about 50 Angstroms, circuits for high speed devices with a relatively thin gate oxide thickness of about 20 Angstroms and circuits for low power devices with intermediate gate oxide thicknesses are required to operate simultaneously on a substrate. In some cases, more than three different oxide thicknesses may be necessary. Methods of generating more than two oxide thicknesses usually require etch back of unwanted oxide regions resulting in undesirable STI corner loss. Moreover, a large gate leakage is observed on the thinnest oxides. Therefore, an improved method of making multiple gate oxide thicknesses is needed. The improved method should minimize STI corner loss caused by etching, lower the leakage current for thin oxide layers, and prevent boron mobility between the gate electrode and underlying channel. An improved process will also avoid nitridation of a silicon substrate that leads to a poor silicon/silicon oxide interface and reduced ion mobility.
A recent technology called embedded DRAM or e-DRAM involves a combination of memory and logic functions on a chip. Memory circuits require an effective gate oxide thickness of about 50 Angstroms while low power circuits require an effective gate oxide thickness of 12 to 15 Angstroms and high performance circuits need an effective gate oxide thickness in the range of 8 to 12 Angstroms. Traditional ultra-thin silicon dioxide gates are unacceptable because of a high leakage current and a high mobility of doped impurities such as boron between the gate electrode and channel regions. Therefore, an improved method of making e-DRAM devices is needed so that higher performance can be combined with high reliability to satisfy the demand of new technologies.